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DATA SHEET
MOS INTEGRATED CIRCUIT
PD23C256112A
NAND INTERFACE 256M-BIT MASK-PROGRAMMABLE ROM
Description The PD23C256112A is a 256 Mbit NAND interface programmable mask read-only memory that operates with a single power supply. The memory organization consists of (512 + 16 (Redundancy)) bytes x 32 pages x 2,048 blocks. The PD23C256112A is a serial type mask ROM in which addresses and commands are input and data output serially via the I/O pins. The PD23C256112A is packed in 48-pin PLASTIC TSOP(I). Features * Word organization (33,554,432 + 1,048,576 * Page size (512 + 16 * Block size (16,384 + 512
Note Note Note
) words by 8 bits
) by 8 bits
) by 8 bits
Note Underlined parts are redundancy. Caution Redundancy is not programmable parts and is fixed to all FFH. * Operation mode READ mode (1), READ mode (2), READ mode (3), RESET, STATUS READ, ID READ * Operating supply voltage : VCC = 3.3 0.3 V * Access Time Memory cell array to starting address Read cycle time /RE access time * Operating supply current During read : 30 mA (MAX.) (50 ns cycle operation) During standby (CMOS) : 100 A (MAX.) Ordering Information Part Number : 7 s (MAX.) : 50 ns (MIN.) : 35 ns (MAX.)
Package 48-pin PLASTIC TSOP(I) (12x18) (Normal bent) 48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
PD23C256112AGY-xxx-MJH PD23C256112AGY-xxx-MKH
(xxx : ROM code suffix No.)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M15902EJ2V0DS00 (2nd edition) Date Published September 2002 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
(c)
2001
PD23C256112A
Pin Configurations /xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12x18) (Normal bent) [ PD23C256112AGY-xxx-MJH ]
Marking Side
NC NC NC IC IC GND R, /B /RE /CE NC NC VCC VSS NC NC CLE ALE /WE IC IC IC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VCC VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC
I/O0 to I/O7 CLE ALE /WE /RE /CE R, /B VCC Vss NC IC
Note2 Note3 Note1
: Address Inputs / Command Inputs / Data Outputs : Command Latch Enable Input : Address Latch Enable Input : Write Enable Input : Read Enable Input : Chip Enable Input : READY, /BUSY Output : Supply voltage : Ground : No connection : Internal connection : GND
GND
Notes 1. This pin is an open-drain output pin. Therefore, a pull-up resistor is required when using this pin. 2. Some signals can be applied because this pin is not connected to the inside of the chip. 3. Leave this pin unconnected or connected to VSS.
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M15902EJ2V0DS
PD23C256112A
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent) [ PD23C256112AGY-xxx-MKH ]
Marking Side
NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VCC VSS NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC NC NC IC IC GND R, /B /RE /CE NC NC VCC VSS NC NC CLE ALE /WE IC IC IC NC NC NC
I/O0 to I/O7 CLE ALE /WE /RE /CE R, /B VCC Vss NC IC
Note2 Note3 Note1
: Address Inputs / Command Inputs / Data Outputs : Command Latch Enable Input : Address Latch Enable Input : Write Enable Input : Read Enable Input : Chip Enable Input : READY, /BUSY Output : Supply voltage : Ground : No connection : Internal connection : GND
GND
Notes 1. This pin is an open-drain output pin. Therefore, a pull-up resistor is required when using this pin. 2. Some signals can be applied because this pin is not connected to the inside of the chip. 3. Leave this pin unconnected or connected to VSS.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15902EJ2V0DS
3
PD23C256112A
Input / Output Pin Functions
Pin name Input / Output Function I/O port for address input, command input, and data output. I/O pins.
Input, Output I/O0 to I/O7 (Address Inputs / Command Inputs / Data Outputs) CLE (Command latch Enable Input) ALE (Address latch Enable Input) /WE (Write Enable Input) /RE (Read Enable Input) /CE (Chip Enable Input) R, /B (READY, /BUSY Output) Input
Input pin for signal for controlling loading of commands to command register in device. By making this signal high level at the rising edge or falling edge of the /WE signal, the data of the I/O0 to I/O7 pins is loaded to the command register as commands. Input pin for signal for controlling loading of address data to the address register in the device. By making this signal high level at the rising edge or falling edge of the /WE signal, the data of the I/O0 to I/O7 pins is loaded as address. Input pin for signal for loading the data from the I/O0 to I/O7 pins inside the device. Input pin for signal for serially outputting data. The output data of I/O0 to I/O7 is determined after tREA from the falling edge of the /RE signal, and the internal address counter is incremented by +1 at the rising edge of the /RE signal. Input pin for device selection signal. During read, the standby mode is entered by making this signal high level. Output pin for signal that notifies the internal operating status of the device to external. This is an open-drain output signal. During read, Busy is output during operation (R, /B = low level), and upon completion, Ready (R, /B = high level) is automatically output.
Input
Input Input
Input Output
4
Data Sheet M15902EJ2V0DS
PD23C256112A
Block Diagram
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Status Register
Dara Register Circuit
Input / Output Buffer
Sense Amplifier ID Register
Address Register Command Register
Y-Selector
X-Decoder
/CE CLE ALE /WE /RE
Memory Cell Matrix
Control Logic
READ Contorol Circuit
READY/BUSY Control Circuit
Vcc Vss
R, /B (Open-drain)
Data Sheet M15902EJ2V0DS
5
PD23C256112A
Memory Area
1 Page = 528 Bytes 0 0 1 2
* 1 Block = 32 Pages * * * * *
255 256
*
*
*
511
* 527
30 31
* * * * * * * * *
(A)
(B)
(C)
2,048 Blocks = 65,536 Pages
65,533 65,534 65,535 512 Bytes (Main memory) 16 Bytes (Redundancy)
* The start address (SA) during read operation is specified divided into three areas using three types of read commands. In read mode (1), start address (SA) is set in area (A). In read mode (2), start address (SA) is set in area (B). In read mode (3), start address (SA) is set in area (C).
One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy). One block consists of 32 pages.
Caution The data of area (C) is redundancy. Redundancy is not programmable parts and is fixed to all FFH.
6
Data Sheet M15902EJ2V0DS
PD23C256112A
Operation Modes
Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are controlled by the CLE, ALE, /WE, /RE, and /CE signals.
Command input cycle
Address input cycle
Serial read cycle
CLE
/CE
/WE
ALE
/RE
I/O0 to I/O7
High-Z
High-Z
High-Z
R, /B
Busy
Operation mode
Mode Command input cycle Address input cycle Serial read cycle CLE H L L ALE L H L /CE L L L H /WE /RE H H
Operation mode during serial read
Mode Data output Output High-Z Standby CLE L L L ALE L L L /CE L L H /WE H H H /RE L H x I/O0 to I/O7 Data output High-Z High-Z
Remark x : VIH or VIL
Data Sheet M15902EJ2V0DS
7
PD23C256112A
Operation Commands
The following six operation settings are possible by inputting commands from I/O pins.
Command Read mode(1) Read mode(2) Read mode(3) Reset Note2 Status read ID read
Note3 Note1
HEX 00H 01H 50H FFH 70H 90H
I/O7 L L L H L H
I/O6 L L H H H L
I/O5 L L L H H L
I/O4 L L H H H H
I/O3 L L L H L L
I/O2 L L L H L L
I/O1 L L L H L L
I/O0 L H L H L L
Command receivable during Busy
Notes 1. The data output in read mode (3) is all FFH. 2. The only command that can be executed when the device is Busy is the reset command. Do not set any of the other commands while the device is Busy. 3. For ID read, input "00H" during the first address cycle after setting a command.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]
Command 1st address cycle 2nd address cycle 3rd address cycle I/O7 A7 A16 A24 I/O6 A6 A15 A23 I/O5 A5 A14 A22 I/O4 A4 A13 A21 I/O3 A3 A12 A20 I/O2 A2 A11 A19 I/O1 A1 A10 A18 I/O0 A0 A9 A17
(2) When 50H command is set [Read mode (3)]
Command 1st address cycle 2nd address cycle 3rd address cycle I/O7 x A16 A24 I/O6 x A15 A23 I/O5 x A14 A22 I/O4 x A13 A21 I/O3 A3 A12 A20 I/O2 A2 A11 A19 I/O1 A1 A10 A18 I/O0 A0 A9 A17
Remarks 1. A0 to A24 are internal addresses. 2. Internal address A8 is set internally with command 00H or 01H. 3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address cycle are VIH or VIL.
8
Data Sheet M15902EJ2V0DS
PD23C256112A
Usage Cautions
(1) Rated operation Operation using timing other than shown in the timing charts is not guaranteed.
(2) Commands that can be input The only commands that can be input are 00H, 01H, 50H, 70H, 90H, and FFH. Do not input any other commands. If other commands are input, the subsequent operation is not guaranteed.
(3) Command limitations during Busy period Do not input commands other than the reset command (FFH) during the Busy period. If a command is input during the Busy period, the subsequent operation is not guaranteed.
(4) Cautions regarding /RE clock * Following the last /RE clock, do not input the /RE clock until the R, /B pin changes from Busy to Ready. * Do not input the /RE clock other than during data output.
(5) Cautions upon power application Since the state of the device is undetermined upon power on, input high level to the /CE pin and execute the reset command following power on.
(6) Cautions during read mode * Perform address input immediately following command input. If address input is done without performing command input first, the correct data cannot be output because the operation mode is undetermined. * To execute the read mode after the read mode has been stopped with the reset command (FFH) and /CE, input again a command and address.
(7) Busy output following access of last address in page in read mode After the access to the last address in a page, if the delay (tRHCH) from /RE to /CE is 30 ns or less, the Ready status is maintained and Busy is not output by keeping /CE high level for a set period (tCEH).
tCEH
/CE
tRHCH /RE 526 527
R, /B
Data Sheet M15902EJ2V0DS
9
PD23C256112A
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VI VI/O TA Tstg Condition Rating -0.5 to +4.6 -0.3 to VCC+0.3 -0.3 to VCC+0.3 ( 4.6) 0 to 70 -65 to +150 Unit V V V C C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Capacitance (TA = 25C)
Parameter Input capacitance Output capacitance Symbol CI CO f = 1 MHz Test condition MIN. TYP. MAX. 10 10 Unit pF pF
DC Characteristics (TA = 0 to 70C, VCC = 3.3 0.3 V)
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Output leakage current Power supply current in read Power supply current in command input Power supply current in address input Standby current (TTL) Standby current (CMOS) (R, /B) pin output current Symbol VIH VIL VOH VOL ILI ILO ICCO1 ICCO3 ICCO5 ICCS1 ICCS2 IOL(R, /B) IOH = -400 A IOL = 2.1 mA VI = 0 V to VCC VO = 0 V to VCC /CE = VIL, IOUT = 0 mA, tCYCLE = 50 ns tCYCLE = 50 ns tCYCLE = 50 ns /CE = VIH /CE = VCC - 0.2 V VOL = 0.4 V 8 Test conditions MIN. 2.0 -0.3 2.4 0.4 10 10 30 30 30 1 100 TYP. MAX. VCC + 0.3 +0.8 Unit V V V V
A A
mA mA mA mA
A
mA
10
Data Sheet M15902EJ2V0DS
PD23C256112A
AC Characteristics (TA = 0 to 70C, VCC = 3.3 0.3 V)
Parameter CLE setup time CLE hold time /CE setup time /CE hold time Write pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time /WE high hold time Ready to /RE falling edge Read pulse width Read cycle time /RE access time (serial data access) /CE high hold time for last address in serial read cycle /RE access time (ID read ) /RE high to output High-Z /CE high to output High-Z /RE high hold time Output High-Z to /RE falling edge /RE access time (status read) /CE access time (status read) /WE high to /CE low /WE high to /RE low ALE low to /RE low (ID read) /CE low to /RE low (ID read) Memory cell array to starting address /WE high to Busy ALE low to /RE low (read cycle) /RE last clock rising edge to Busy (in sequential read) /CE high to Ready (when interrupted by /CE in read mode) Device reset time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREA tCEH tREAID tRHZ tCHZ tREH tIR tRSTO tCSTO tWHC tWHR tAR1 tCR tR tWB tAR2 tRB tCRY
Note
MIN 0 10 0 10 25 0 10 20 10 50 15 20 35 50
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
35 100 35 10 30 20 15 0 35 45 30 30 100 100 7 200 50 200 1 6
ns ns ns ns ns ns ns ns ns ns ns ns ns
s
ns ns ns
s s
tRST
Note tCRY (time from /CE high to Ready) depends on the pull-up resister of the R, /B output pin.
Data Sheet M15902EJ2V0DS
11
PD23C256112A
AC Test Conditions Input waveform (Rise / Fall Time 5 ns)
1.5 V
Test points
1.5 V
Output waveform
1.5 V
Test points
1.5 V
Output load 1 TTL + 100 pF
12
Data Sheet M15902EJ2V0DS
Read Cycle Timing Chart (1) (In case of read mode (1))
CLE
tCLS tCLH
/CE
tCS /WE tALH
Data Sheet M15902EJ2V0DS
tCH
tCS
tWC
tR
tCEH
tALS
tWP
tWH
tALH
tAR2
tCRY tCHZ
ALE
tRR tRC tRC
/RE tWB tDS I/O0 to I/O7 00H tDH tDS A0 to A7 tDS A9 to A16 tDS A17 to A24 High-Z DOUT N tREA tRP tREH tRHZ DOUT N+1 DOUT 527 tRB tRHZ High-Z
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Output page M data
Remarks 1. Start address (SA) specification when read is performed with command 00H. N: 0 to 255 2. Then time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R,/B output pin.
13
14
Read Cycle Timing Chart (2) (In case of read mode (2))
CLE
tCLS tCLH
/CE
tCS /WE tALH
Data Sheet M15902EJ2V0DS
tCH
tCS
tWC
tR
tCEH
tALS
tWP
tWH
tALH
tAR2
tCRY tCHZ
ALE
tRR tRC tRC
/RE tWB tDS I/O0 to I/O7 01H tDH tDS A0 to A7 tDS A9 to A16 tDS High-Z A17 to A24 DOUT 256+N tREA tRP tREH tRHZ DOUT 256+N+1 DOUT 527 tRB tRHZ High-Z
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Output page M data
Remarks 1. Start address (SA) specification when read is performed with command 01H. N: 0 to 255 2. Then time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R,/B output pin.
Read Cycle Timing Chart (3) (In case of read mode (3))
CLE
tCLS tCLH
/CE
tCS /WE tALH
Data Sheet M15902EJ2V0DS
tCH
tCS
tWC
tR
tCEH
tALS
tWP
tWH
tALH
tAR2
tCRY tCHZ
ALE
tRR tRC tRC
/RE tWB tDS I/O0 to I/O7 50H tDH tDS A0 to A3 tDS A9 to A16 tDS A17 to A24
High-Z
tRP
tREH tRHZ tRHZ DOUT 512+N+1 DOUT 527 tRB
High-Z
DOUT 512+N tREA
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Output page M data
Remarks 1. 2. 3. 4.
Start address (SA) specification when read is performed with command 50H. N: 0 to 15 The start address of area C (redundancy data) is specified with A0 to A3 during the 1st address cycle. At this time, A4 to A7 are Don't Care. The time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R, /B output pin. The data that is output is FFH.
15
16
Read Cycle Timing Chart (4) (When /CE is made high level in the read mode)
CLE
tCLS
/CE
tCLH
tCS /WE
tCH
tCS
tWC
tR
tALH
Data Sheet M15902EJ2V0DS
tALS
tWP
tWH
tALH
tAR2 tCHZ
ALE
tRR
tRC
tRC
/RE tWB tDS I/O0 to I/O7 tDH tDS
Address input
tRP
tREH tRHZ
tRHZ
tDS
Address input
tDS
Address input
Command input
High-Z
DOUT N tREA
DOUT N+1
DOUT N+2
High-Z
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Remark If /CE is made high level during the read cycle, the read operation until that time is cancelled. Therefore, to perform read again, execute a new command and new address input.
PD23C256112A
Sequential Read
In read modes (1), (2), and (3), when a command (00H, 01H, 50H) is input and an address specified, if it is in the block that includes the address that was specified first, the address is automatically incremented and the read operation is continuously performed until the last address in the same block, by inputting the /RE clock. At this time, a Busy period (tR) occurs after the last address is accessed in a page.
Command input Address 00H 01H 50H tR R, /B Busy Busy Busy Busy Busy Busy tR tR tR tCRY Note input Command Output of in last page input Address in block input 00H 01H 50H tR
Note
Page M data output
Page M+1 data output
Data output
In same block (Maximum of 32 pages)
Note To perform read again after reading the 527th byte of data of the last page of block, stop the read operation once, and then restart the read operation by inputting again the read command and an address.
Relationship Between Command and Start Address (SA) during Sequential Read
(A) 0 256 (B) (C) 512 527 0 (A) 256 (B) (C) 512 527 0 (A) 256 (B) (C) 512 527
SA SA SA
1 block = 32 pages
Sequential read mode (1) (When "00H" command is input)
Sequential read mode (2) (When "01H" command is input)
Sequential read mode (3)Note (When "50H" command is input)
Note When the "50H" command is set, only the (C) area (redundancy data part) is continuously read.
* When the "00H" command is set, the start address (SA) is set to area (A). * When the "01H" command is set, the start address (SA) is set to area (B). * When the "50H" command is set, the start address (SA) is set to area (C).
Data Sheet M15902EJ2V0DS
17
18
Sequential Read Cycle Timing Chart (1) (In case of read mode (1))
CLE
tCLS tCLH
/CE
tCS /WE tALH
Data Sheet M15902EJ2V0DS
tCH
tCS
tWC
tR
tALS
tWP
tWH
tALH
tAR2
ALE
tRR tRC tRC
/RE tR tWB tDS I/O0 to I/O7 00H tDH tDS A0 to A7 tDS A9 to A16 tDS A17 to A24 High-Z DOUT N tREA tRP tREH tRHZ DOUT N+1 DOUT 527 tRB High-Z DOUT 0 High-Z DOUT 1 tRR
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Output page M data
Access page M+1
Output page M+1 data
Remark Start address (SA) specification when read is performed with command 00H. N: 0 to 255
Sequential Read Cycle Timing Chart (2) (In case of read mode (2))
CLE
tCLS tCLH
/CE
tCS /WE tALH
Data Sheet M15902EJ2V0DS
tCH
tCS
tWC
tR
tALS
tWP
tWH
tALH
tAR2
ALE
tRR tRC tRC
/RE tR tWB tDS I/O0 to I/O7 01H tDH tDS A0 to A7 tDS A9 to A16 tDS A17 to A24 High-Z DOUT 256+N tREA tRP tREH tRHZ DOUT 256+N+1 DOUT 527 tRB High-Z DOUT 0 High-Z DOUT 1 tRR
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Output page M data
Access page M+1
Output page M+1 data
Remark Start address (SA) specification when read is performed with command 01H. N: 0 to 255
19
20
Sequential Read Cycle Timing Chart (3) (In case of read mode (3))
CLE
tCLS tCLH
/CE
tCS /WE tALH
Data Sheet M15902EJ2V0DS
tCH
tCS
tWC
tR
tALS
tWP
tWH
tALH
tAR2
ALE
tRR tRC tRC
/RE tR tWB tDS I/O0 to I/O7 50H tDH tDS A0 to A3 tDS A9 to A16 tDS High-Z A17 to A24 DOUT 512+N tREA DOUT 512+N+1 tRP tREH tRHZ DOUT 527 tRB High-Z DOUT 512 High-Z DOUT 513 tRR
tDH R, /B
tDH
tDH
PD23C256112A
Access page M
Output page M data
Access page M+1
Output page M+1 data
Remark Start address (SA) specification when read is performed with command 50H. N: 0 to 15
PD23C256112A
Status Read
Status information can be output from the I/O pins with the /RE clock following input of the 70H command. Status read is a function to recognize the status of the device from external.
tCLS tCLS tCLH
CLE
/CE
tCS /WE tWP /RE tDS I/O0 to I/O7 tDH tWHC tRHZ tWHR tIR High-Z Status tRSTO R, /B Ready High-Z tCH tCSTO
tCHZ
70H
Status I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Ready / Busy Not used Not used Not used Not used Not used Ready / Busy Write protect
Status output data Note 0/1 0 0 0 0 0 1/0 0
Note Use the status read command only during Ready.
Data Sheet M15902EJ2V0DS
21
PD23C256112A
ID Read
To recognize the ID code (maker code / device code) of this device in a system, execute the ID read command. The ID code can be read with the following timing.
tCLS
CLE
tCLS tCLH
/CE
tCS /WE tALH tALS tWP tALH tAR1 tCH tCS tCH tCR
ALE tRC /RE tRP tDS I/O0 to I/O7 tDH tDS tDH Maker code 90H 00H High-Z 10H tREAID tREAID Device code 58H tREH
I/O7 Maker code Device code L L
I/O6 L H
I/O5 L L
I/O4 H H
I/O3 L H
I/O2 L L
I/O1 L L
I/O0 L L
HEX 10H 58H
Cautions 1. If the /RE clock is input after the maker code and device code are output, the output data is not guaranteed. Therefore, do not input the /RE clock following device code output. 2. Do not input an address other than 00H after setting the ID read command (90H). If an address other than 00H is input, the data following /RE clock input is not guaranteed.
22
Data Sheet M15902EJ2V0DS
PD23C256112A
Reset Cycle Timing Chart
CLE
tCLS tCLH
/CE
tCS /WE tRST tALS ALE tDS I/O0 to I/O7 FFH tWB R, /B tDH tWP tALH tCH
Data Sheet M15902EJ2V0DS
23
PD23C256112A
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
1 48 F G R detail of lead end
Q 24 25 E P I J A
L S
S D K N S
C MM
B
NOTES
1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM A B C D E F G I J K L M N P Q R S
MILLIMETERS 12.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 1.00.05 16.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 18.00.2 3 +5 -3 0.25 0.600.15 S48GY-50-MJH1-1
24
Data Sheet M15902EJ2V0DS
PD23C256112A
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end 1 48 E S Q L
R G F
24
25
K
N
S S
D C
MM B
I P
J
A
NOTES
1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM A B C D E F G I J K L M N P Q R S
MILLIMETERS 12.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 1.00.05 16.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 18.00.2 3 +5 -3 0.25 0.600.15 S48GY-50-MKH1-1
Data Sheet M15902EJ2V0DS
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PD23C256112A
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD23C256112A.
Types of Surface Mount Device
PD23C256112AGY-MJH : 48-pin PLASTIC TSOP(I) (12x18) (Normal bent) PD23C256112AGY-MKH : 48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
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Data Sheet M15902EJ2V0DS
PD23C256112A
Revision History
Edition/ Date 2nd edition/ Sep. 2002 p.4 p.9 p.4 p.23 Modification Modification Input/Output Pin Functions Usage Cautions This edition p.1 Page Previous edition p.1 Type of revision Location Description (Previous edition This edition)
Modification
Features
Read cycle time: 50ns(MAX.) 50ns(MIN.) Signal DescriptionsInput/Output Pin Functions Moved in front of Electrical Specifications page
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Data Sheet M15902EJ2V0DS
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Data Sheet M15902EJ2V0DS
PD23C256112A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD23C256112A
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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